1. Technical Field
The embodiments described herein relate to semiconductor integrated circuits and, in particular, to a frequency adjusting apparatus that can reduce electromagnetic interference and a DLL circuit including the same.
2. Related Art
A DLL (delay locked loop) circuit provided in a conventional semiconductor integrated circuit is used to provide an internal clock signal having a phase that leads the phase of a reference clock signal obtained by buffering an external clock signal by a predetermined amount of time. When an internal clock signal used in the semiconductor integrated circuit is delayed by a clock signal buffer and a transmission line, a phase difference between the external clock signal and the internal clock signal occurs, which increases the data access time to output data. The DLL circuit is used to solve this problem.
A conventional DLL circuit controls the phase of the internal clock signal to lead the phase of the external clock signal by a predetermined amount of time to widen such an effective data output period. In recent years, as a high-speed and highly integrated semiconductor integrated circuits are needed, electromagnetic interference (EMI) is attracting attention as a matter of great importance. The electromagnetic interference remarkably occurs when each clock signal or each signal has a prescribed, accurate frequency; however, to date, there is no technology that can solve such a problem.